Schottky Barrier CMOS Scalable, Lower Cost, Radiation Tolerant, High Performance Technology for Sub-25nm Gate Lengths Technology Overview

Spinnaker Semiconductor has demonstrated and continues to develop a patent-protected metal source/drain Schottky barrier MOS technology (SBMOS). The SBMOS transistor architecture replaces the impurity doped source and drains of conventional silicon MOS with metal. This simple change provides numerous performance, manufacturability and cost advantages compared to competing silicon CMOS architectures for the physical gate length technology nodes below 45 nm. Sub-30nm PMOS and NMOS devices have been fabricated at MIT-Lincoln Lab. Non-optimized PMOS devices nearly meet roadmap drive and leakage current requirements for high performance logic applications and are competitive with the current state-of-the-art for this channel-length regime. Extremely high fT is measured up to 300 GHz for sub-30nm PMOS devices, which to the best of our knowledge, is the highest fT reported to date for silicon MOS transistors. The metal source-drain SBMOS architecture provides numerous and broad benefits, which are highly relevant considering the industry’s roadmap and technology challenges in both the near and long term. Technology benefits include scalability to the sub-10nm channel length regime; less than 10 Ω−μm total source-drain parasitic series resistance; channel mobility enhancement; and inherent tolerance to radiation effects including unconditional elimination of latchup and significant reduction of soft-error rates. Remarkably, this is accomplished using a manufacturing process that is simpler and requires fewer masks than conventional silicon CMOS, a feature not found in other competing transistor technologies. The process is 100% compatible with existing silicon CMOS factories and with new industry innovations including SOI, strained silicon, metal gates, and high K dielectrics. Spinnaker Semiconductor, Inc. © 2004 Page 2 of 12